As is well known, one of the main difficulties that are encountered when producing memory devices integrated on semiconductors on very large-scale basis is the yield of the respective production process. It happens indeed that at the end of the production process, the defectiveness of the memory cell matrix is such to render the device not usable. The cell matrix takes up the prevalent part of the circuitry area of the memory device and the probability is therefore very high that a serious production defect could arise just in the circuitry portion taken up by the matrix.
As the integrated memory devices of EPROM and flash type have a relatively low yield, the prior art has tried to find a remedy for this drawback by equipping the cell matrix with additional rows and/or columns that can be used to replace defective rows or columns that show malfunction following the testing of the device. In order to use the redundant rows and columns it is necessary to have memory elements, called UPROM cells available for the addressing of redundancy.
Those skilled in the art have a through knowledge of the design and use techniques of the redundancy rows and columns and of the respective selection circuitry. The latter allows a re-addressing of the memory in such a way to replace the addresses containing defective bits with the functioning ones existing in the redundancy rows or columns.
At present, the continuous evolution of the technology and the general trend to cost reduction in the semiconductor market leads to the design of memory devices that, their performance being equal, take up a smaller circuit area.
In FIG. 1 there is shown a schematic view of a UPROM redundancy cell realized according to the prior art.
The UPROM redundancy cell comprises at least one memory element P0 of EPROM or Flash type, which has a control terminal and a conduction terminal X to be driven. The cell furthermore includes a latch register constituted of two inverters I1, I2 connected to the memory element, as well as MOS transistors (represented by M2) which connect the memory element to a power supply reference Vdd at low voltage.
In a first power-up phase, by means of a transistor M16 receiving a high signal POR, the latch is unbalanced in such a way to have a logic "0" on the side of the "q" node and a logic "1" on the side of the "latch" node.
If the Flash cell P0 was written, i.e., if its threshold voltage was greater than 4 or 5 V, it would not absorb current and therefore the latch would stay in its state of rest.
If instead the Flash cell P0 is erased, i.e., if it has a threshold voltage lower than 2.5 V, it will start to conduct when the two voltage values UGV and Vb will have reached their steady state operation value, equal to about 3 V and 1.5 V respectively. At this point latch 2 could be unbalanced and taken into a state in which the I1 inverter output is at a high logic value while the I2 inverter output is at a low logic value.
Even if advantageous upon different points of view, this solution does not offer particularly reduced dimensions as it requires as cell equipment various types of transistors to carry out the different operations of set, reset, reading and programming.